1. Field of Invention
This invention relates to a phase-locked loop (PLL) and a method for controlling the PLL, and particularly relates to restarting a voltage-controlled oscillator (VCO) of the PLL.
2. Description of Related Art
FIG. 1 schematically illustrates a conventional PLL 100. The PLL 100 includes a phase detector 110, a charge pump 120, a low-pass filter 130, a VCO 140, a feedback frequency divider 150, and an output frequency divider 160. Due to the feedback frequency divider 150 and the output frequency divider 160, the PLL 100 is capable of generating an output clock signal CLKB with arbitrary frequency based on an input clock signal CLKA.
The PLL 100 needs a power down signal PD to reset the PLL 100 and starts up the VCO 140 initially in order to avoid a non-oscillating mode of the PLL 100. In the non-oscillating mode, the output of the VCO 140 does not oscillate and therefore the PLL 100 does not work.
It is possible that the PLL 100 enters the non-oscillating mode in runtime after the initial startup. In this situation, the power down signal PD may be sent to restart the charge pump 120, the low-pass filter 130, and the VCO 140 to resume the normal operation of the PLL 100. However, such a restart is slow because several elements of the PLL 100 have to be restarted. In addition, the power down signal PD is an external signal. The power down signal PD is not generated by any internal signal of the PLL 100. Therefore, the power down signal PD is slow in response and cannot restart the oscillation of the PLL 100 in real time.